module key_filter(
	input wire clk,
	input wire rst_n,
	input wire key_in,
	input wire [7:0]filter_canshu,
	output reg key_out
	);

reg [15:0] counter;

always @(posedge clk) 
begin
	if (!rst_n) begin
		counter<=0;
		key_out<=key_in;
		end
	else begin
		if(key_in==key_out)
			counter<=(filter_canshu<<8);
		else
			if(counter!=0)
				counter<=counter-1;
			else
				key_out<=key_in;
		end
end
endmodule